circuit note CN-0140 circuit designs using analog devices products apply these product pairings quickly and with confidence. for more information and/or support call 1 -800- analogd (1 -800-262-5643) or visit www.analog.com/circuit . devices connected /referenced adl5356 1.2 ghz to 2.5 ghz, dual - balanced mixer, lo buffer, if amplifier, and rf balun ad8376 ultralow distortion if dual vga ad9258 14- bit, 125 msps, 1.8 v dual adc ad9517 -4 12- output clock generator with integrated 1.6 ghz vco high performance, dual channel if sampling receiver rev. 0 circuits from the lab from analog devices have been designed and buil t by analog devices engineers. standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a l ab environment at room temperature. however, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. accordingly, in no event shall analog devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any circuit from the lab . (continued on last page) one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 analog devices, inc. all rights reserved. circuit function and benefits th is circuit is a high performance , dual channel if sampling receiver, also called a main and diversity receiver in base station terminology . the d ow nconverting receiver uses a single if frequency of 153.6 mhz and includes a dual downconverting mixer, digitally controlled dual vga, dual adc, and clock synthesizer. the circuit takes an incoming rf waveform and outputs a dual 14 - bit resolution digital data stream. it is optimized for high frequency if sampling and provides exceptional spurious - free dynamic range (sfdr) performance of 79.61 dbc with a sampling rate of 122.88 msps at the high gain setting . circuit description th is circuit includes the r f front end , as well as the if sampling receiver. it is composed of a dual balanced mixer, broadband if saw filter, digitally controlled dual vga , and dual adc. the circuit also includes a synthesizer , which generates the adc sampling clock . the adl5356 dual balanced mixer is designed to downconvert radio frequencies (rf) primarily between 1200 mhz and 2500 mhz to lower intermediate frequencies (if) between 30 mhz and 450 mhz. 5 18pf 18pf 18pf 5v 5v 5v 18pf 58nh 72nh 470pf 470pf 0.1f 0.1f 57.6 ? 470pf 100pf 1.5k ? 430? 200? 200? 10nf 50? 0.1f 0.1f 0.1f 0. 22f refin out0 cp bypass lf 1/2 ad8376 309? 3.3pf a0 to a4 20pf 1h 1h 330nh 330nh 330nh 330nh cml 165? 165? cml clk+ 122.88mhz clkC 56nh 33? 33? 1/2 ad9258 08713-001 5v 1.21k ? gm in ct on op lg 330nh 330nh 390? 50? lo in 1796.4mhz ref in 30.72mhz 5v 5v losw loi2 22pf 22pf 50? 10nf 10pf rf in 1950mhz 1/2 adl5356 153.6mhz f c = 153.6mhz bw = 20mhz epcos b5206 saw filter 1.8v avdd 3v 1.8v dvdd 14 1:1 ad9517-4 refin out0 notes 1. all pins and connections to adl5356, ad8376, ad9258 and ad9417 not shown. consult product data sheets for detailed information. figure 1. broadband dual channel if sampling receiver (simplified schematic: only one - half of the receiver i s shown. all connections and decoupling not shown)
CN-0140 circuit note rev. 0 | page 2 of 4 the rf and lo input ports are al ready ac - coupled to prevent non zero dc voltag es from damaging the rf balun or lo input circuit s, which are part of the adl5356 . the adl5356 is configured for single- ended lo operation with a recommended lo drive of 0 dbm. with the losw pin of the mixer grounded, only one of the two lo channels (loi2) is used in this circuit. the mixer differential if interface requires pull - up choke inductors to bias the open - collector outputs and to set the output impedance match. the shunting impedance of the choke inductors used to couple dc current into the if amplifier should be selected to provide the desired output return loss. the real part of the mixer output impedance is approximately 200 ?, which matches many commonly used saw filters without the need for a transformer. the receiver channel filtering is mainly performed by a 153.6 mhz, 20 mhz bandwidth epcos model b5206 saw f ilte r which follows the mixer. the typical insertion loss ( il ) of this filter is about 9 db. the natural matched impedance o f this saw filter is 100 ? differential. a simple l-c reactive network matches the saw filter to the mixer 200 ? differential output and the ad8376 vga 150 ? differential input impedance. ta ble 1 highlights the cascaded performance of the dual mixer plus saw filter. note that ip3 is the third - order intercept point ; ip1db is the input referred ?1 db compression point ; and nf is the noise figure. a receiver gain control of 24 db is provided by the ad8376 dual, high output linearity vga that is optimized for adc interfacing. two independent 5 - bit binary codes change each attenuator setting in 1 db steps such that the gain of each amplifier can be set from +20 db to ?4 db. the output third order intercept point ( ip3 ) and noise floor essentially remain constant across the 24 db available gain range. this is a valuable feature in a variable gain re ceiver where it is desirable to maintain a constant instantaneous dynamic range as the receiver gain is modified. the output ip3 of the ad8376 an d the subsequent anti aliasing filter is in excess of 50 dbm with a 2 v p- p composite signal. the ad8376 provid es a 1 50 input impedance and is tuned to drive a 150 load impedance. the open - collector output structure requires dc bias through an external bias network. a set of 1 h choke inductors are used on each channel output to provide bias to the open -colle ctor output pins . an optimized differential fourth order band -pass antialias ing filter is implement ed at the dga outputs before analog - to - digital conversion. note that the antialiasing filter is terminated with shunt input and output resistances of about 3 00 . the shunt resistances at either end of the filter, 309 at the input and 330 (through two 165 bias setting resistors) at the output, combine to present the ad8376 with a nominal 150 load impedance. the band - pass antialiasing attenuates the output noise of the ad8376 outside of the intended nyquist zone. in general, the snr improves several db by including a reasonable order antialiasing filter. the antialiasing filter is comprised of a fourth order butterworth filter with a resonant tank circui t. the resonant tank helps ensure that the adc input looks like a real resistance at the target center frequency by resonating out the capacitive portion of the adc load (see an - 742 and an - 827 application notes ). in addition, the ac - coupling capacitors and the bias chokes introduce additional zeros into the transfer function. the overall frequency response takes on a band -pass characteristic, helping to reject noise outside of the intended nyquist zone. the filter provides a 20 mhz pass band centered at 153.6 mhz with 0.3 db flatness and an insertion loss of about 3 db. the adc utilized is the 14 - bit ad9258 , which samples at rates up to 125 msps. the ad9258s analog inputs are driven by the ad8376 through the band - pass antialiasing filter. the adc sampling rate is set to 122.88 msps with a full -scale input range of 2 v p- p. the ad92 58 differential clock signal is provided by the ad9517 - 4, a clock generation ic with on - chip vco . the lvpecl level output, out0, is used for low jitter . the ad9517 -4 uses its internal vco frequency of 1474.56 mh z to derive the 122.88 mhz output clock to the adc. a loop filter, designed with the adisimclk ? simulation software , provides a 60 khz cutoff frequency and 50 of phase margin, giving timing jitter of about 160 fs rms . this jitter corresponds to a theoretical snr of 7 6 db , assuming a 153.6 mhz input, using the formula snr = 20 log(1/2 f in t j ). using this circuit, exceptional sfdr performance of 7 9.61 dbc at 153.6 mhz is achieved at maximum gain, as shown in figure 2 . table 1 . c ascaded performance of the dual mixer plus saw filter ( rf =1950 mhz, lo = 1796.4 mhz, if = 153.6 mhz, rf power = ? 10 dbm, lo power = 0 dbm) gain (db) ip3 (dbm) ip1db (dbm) nf (db) adl5356 8.2 30.0 11.5 9.7 adl5356 + saw ?0.3 28.6 11.7 10.9
circuit note CN-0140 rev. 0 | page 3 of 4 08713-002 figure 2. measured single - tone performance of the circuit in figure 1 for a 1950 mhz rf inp ut signa l. sampling frequency = 122.88 msps, if input = 153.6 mhz common variations front - end lnas and attenuators are not included in this circuit but can easily be interfaced to the 50 ? single- ended rf inputs of the adl5356 mixer . for a complete receiver design, adl5521 / adl5523 lnas may be incorporated. the standard configuration using the adl5356 allows reception of rf signals from 1.2 ghz to 2.4 ghz, but it is possible to use the adl5358 mixer , which covers rf input frequencies from 500 mhz to 1700 mhz. an epcos ( www.epcos.com ) saw filter fol lows the mixer and provides the necessary channel selectivity over a bandwidth ranging from 20 mhz to 40 mhz , depending on the chosen filter. the circuit shown uses a 20 mhz bandwidth, 153.6 mhz centered saw filter (part number: b5206) but can also accommo date other pin - compatible filters. some empirical optimization may be needed to help compensate for actual pcb parasitics in saw filter matching and antialias filter implementation. details of designing the interstage filters can be found in the an - 742 and an - 827 application notes. to ensure repeatability of band response, 1% capacitors are recommended for the saw filter matching components and the anti aliasing filter. in addition, coilcraft 0603cs or similar inductors are recommended. other resistors, capacitors, and inductors can be 10% values . excellent layout, grounding, and decoupling techniques must be utilized in order to achieve the desired performance from the circuits discussed in this note. as a minimum, a 4 - layer pcb should be used with one ground plane layer, one power plane layer, and two signal layers. all ic power pins must be decoupled to the ground plane with low inductance multilayer ceramic capacitors (mlcc) of 0.01 f to 0.1 f (for simplicity, not shown in the diagrams). follow the recommendations on the individual data sheets and in tutorial mt - 101 . the product evaluation boards should be consulted for rec ommended layout and critical component placement. these can be accessed through the product pages for the devices . even though the ad8376 and ad9258 (or other adc) may be powered from different supplies, sequencing is not an issue because the input signal to the adc is ac - coupled. the individual data sheet for the adc should be consulted regarding the proper sequencing of the avdd and the dvdd power supplies (if separate supplies are used).
CN-0140 circuit note rev. 0 | page 4 of 4 learn more an - 742 appl ication note. frequency domain response of switched capacitor adcs . analog devices. an - 827 application note. a resonant approach to interfacing amplifiers to switched - capacitor adcs . analog devices. cn - 0002 circuit note, using the ad8376 vga to drive wide bandwidth adcs for high if ac - coupled applications , analog devices. cn - 0046 circuit note, an ultra low distortion differential rf/if front - end for high speed adcs , analog devices. kester, walt. high speed system applic ations , chapter 2 optimizing data converter interfaces , analog devices, 2006. mt - 007 tutorial, aperture time, aperture jitter, aperture delay time removing the confusion , ana log devices. mt - 031 tutorial, grounding data converters and solving the mystery of "agnd" and "dgnd" , analog devices. mt - 073 tutorial, high speed variable gain amplifiers (vgas) , analog devices. mt - 075 tutorial, differential drivers for high speed adcs overview , analog devices. mt - 101 tutorial, decoupling techniques , analog devices. d ata sheets and evaluation boards ad837 6 data sheet ad925 8 data sheet ad9258 evaluation board ad9517 - 4 data sheet ad9517 - 4 evaluation board adl535 6 data sheet adl5356 evaluation board revision history 1 /10 revision 0: initial version (continued from first page) "circuits from the lab" are intended only for use with analog devices products and are the intellectual property of analog de vices or its licensors. while you may use the "circuits from the lab" in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectua l property by application or use of the "circuits from the lab". information furnished by analog devices is believed to be accurate and reliable. however, "circuits from the lab" are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purp ose and no responsibility is assumed by analog devices for their use, nor for any infringements of patents or other rights of third parties that may result from t heir use. analog devices reserves the right to change any "circuits from the lab" at any time without notice, but is under no obligation to do so. trademarks and registered trademarks are the property of their respectiv e owners. ? 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. cn08713 -0- 1/10(0)
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